Conventionally, an LDD structure has been adopted as the structure of a MOS transistor in order to suppress a short channel effect and improve hot carrier immunity and the like.
On the other hand, with the progress of the scaling down and high integration of a semiconductor device, a reduction in gate length is promoted in the MOS transistor. However, due to the reduction in gate length, the influence of parasitic resistance of source/drain becomes manifest. Hence, to deal with this, a MOS transistor having a so-called extension structure is devised. In this MOS transistor, a pair of impurity diffusion layers are formed by forming shallow extension regions, thereafter forming sidewalls or the like on a gate electrode, and then forming deep source/drain regions so as to partly overlap with the extension regions.
However, recently, further scaling down and high integration of the MOS transistor have been progressing rapidly, and the following two problems emerge from the MOS transistor having the extension structure.
(1) For further scaling down of the MOS transistor, a concentration profile of the extension region is important. In particular, a lateral concentration profile in the extension region is a key factor in improving current drive capability. In this case, threshold voltage roll-off characteristics and the current drive capability, that is, electric resistance of the extension region have a so-called trade-off relationship, and it is necessary to minutely adjust these two as shown below.
In order to improve the threshold voltage roll-off characteristics, it is desirable to secure the longest possible metallurgical effective gate length with respect to a provided physical gate length. This makes it possible to set the impurity concentration of a channel low, and thereby scattering of carriers by impurities reduces, which leads to an improvement in mobility, resulting in an improvement in the current drive capability of the MOS transistor. If the metallurgical effective gate length is the same here, the physical gate length can be made shorter as the lateral profile becomes steeper.
Meanwhile, the extension region needs to sufficiently overlap with the gate electrode. The carrier density in an inversion layer in a strong inversion condition reaches the order of 1019/cm, whereby there is a possibility that the extension region directly below an edge of the gate electrode, that is, a tip portion of the extension region functions as an electric resistance and causes a deterioration in current drive capability. To prevent this, it is necessary that the impurity carrier concentration at the tip portion is at least 5×1019/cm3 or more.
To form the extension region where the impurity concentration is controlled as described above, the lateral concentration profile in the extension region needs to be steep. Namely, it is desirable to secure the impurity concentration of 5×1019/cm3 or more at the tip portion and form a concentration profile such that the concentration reduces sharply from the tip portion toward the channel. Ideally, it is suitable to form the extension region in a so-called box shape. However, the lateral concentration profile is generally dominated by a diffusion phenomenon, and therefore it is extremely difficult to control its steepness as desired.
(2) In a present nMOS transistor, arsenic (As) is used as an impurity when the extension region is formed. Arsenic (As) is used since it has a steeper concentration gradient than phosphorus (P) and it is excellent in roll-off characteristics and current drive capability, but there arises a problem that since it is a heavy element, a defect caused at the time of ion implantation does not completely disappear after an annealing process for activation, leading to an increase in components of a source/drain junction leakage and particularly components around the gate electrode.
To suppress a leakage current, it is effective to add annealing to eliminate the defect, but at the same time, the impurity is diffused by annealing, which goes against the scaling down, and hence a different method is needed. A lower power consumption device has a problem that the power consumption by this leakage current is a rate-determining factor, and hence a reduction in power consumption becomes difficult.
Moreover, to prevent the leakage current, P is sometimes used in place of As. However, in the case of P, tail diffusion increases, and hence P cannot be applied to a fine transistor if nothing is done.
As a method for solving the aforementioned problems, concerning a PMOS transistor, a method of adopting nitrogen implantation such as shown in 2002 IEDM 27.3 p. 647-p. 650 and a method of adopting carbon implantation technology as shown in Japanese Patent Application Laid-open No. Hei 10-125916 are published. According to these methods, roll-off is improved. It is known that nitrogen inhibits diffusion of boron (B), and hence roll-off characteristics of the pMOS transistor are improved. Moreover, in the pMOS transistor, the junction leakage also reduces. Carbon has a function of making defects (including interstitial Si) disappear, and hence the roll-off characteristics of the pMOS transistor are similarly improved. Although not described in detail, there is a possibility that a tunneling site which causes the junction leakage disappears and that the leakage current reduces. However, even if so, a fully satisfactory result has not been reached.
Any of the aforementioned prior arts is thought to be effective in the pMOS transistor, but does not produce a marked effect on the nMOS transistor. A primary factor is that in the nMOS transistor, generally arsenic (As) is used in an extension and does not behave like boron (B) or phosphorus (P) which diffuses while pairing up with interstitial Si. Moreover, it is thought to be based, for example, on the fact that in a semiconductor device in which boron is used as an impurity in a pocket region, arsenic inhibits activation of boron, and accelerates diffusion of boron according to conditions.